1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to a method of reducing charging damage to integrated circuits during semiconductor manufacturing. The present invention is particularly suited for ion implant processing in an ion implanter without employing a plasma flood system.
2. Description of the Prior Art
Ion implanters and ion implant process are commonly used in the manufacture of semiconductor products for implanting dopant species into wafers or semiconductor substrates to change the conductivity of the material in such substrates. Ion implanters generally comprise an ion source for generating a beam of ions, a mass analyzer for selecting a particular species of ions from the ion beam and means to direct the mass-selected ion beam through a vacuum chamber onto a target substrate supported on a substrate holder. A high-current ion implanter usually encompasses a plasma flood system used to neutralize positive ions.
Influence of ion implant process on wafers has been investigated. It has been revealed that when processing a wafer in plasma ambient or ion implant process environment, charging damage occurs due to surface charge build-up. Such charging damage to integrated circuits can result in costly losses of product.
Typically, damage to thin insulators such as gate oxide sandwiched between a conductive substrate and isolated conductive electrodes on the surface of a wafer (gates) occurs due to current flow through the insulator, driven by a potential difference between the surface electrode and the substrate. During wafer processing, wafer-scale potential differences are caused by global non-uniformities in plasma density and/or electron temperature or, in the case of ion-beam equipment, by spatially imperfect neutralization of the charging caused by the ion beam.
When devices are under the beam in a high-current ion implanter, they are exposed to positive charging from the high-energy ion beam, from “slow” ions (ionized background gases or the plasma used for charge neutralization), and from secondary electrons emitted from the surface of the wafer due to ionic impact. They are also exposed to negative charging from the “electron shower” or the plasma electrons from a plasma flood system used to neutralize positive charging. Therefore, the net positive charging when devices are under the beam is the sum of the positive and negative charging.
Lukaszek in U.S. Pat. No. 5,998,282 describes a method of reducing charging damage to integrated circuits in ion implant and plasma-based integrated circuit process equipment. Charging damage to integrated circuits during ion implantation and plasma processing of integrated circuit die in a semiconductor wafer is reduced by processing scribe lanes during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lanes during integrated circuit fabrication and reduce current flow through integrated circuit components. Lukaszek also reveals that increasing shunt path current flow within the integrated circuit die is difficult due to circuit layout constraints.